1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and a fabricating method therefor, and more specifically to a non-volatile semiconductor memory having a word line backed or lined with an overlying conductor in order to reduce the resistance of the word line, and a method for forming the word line structure.
2. Description of Related Art
In a flash memory, it is a conventional practice that a word line is backed or lined with an overlying conductor in order to reduce the resistance of the word line. In many flash memories, since a high speed access was not required and since a bit line is formed of a first level interconnection layer, it was sufficient if the word line is backed or lined with an overlying interconnection formed of a second or further high level interconnection metal layer by electrically connecting the word line to the overlying interconnection through contacts which are provided at a rate of one contact per 512 or 1024 cells. Recently, however, with an increasing demand for a flash memory formed together with a microcomputer in a single chip, and therefore, with an increasing demand for the high speed access in the flash memory, it has become necessary to increase the frequency of backing or lining. Here, an example for connecting the word line to a first level metal interconnection through contacts provided at a rate of one contact per 16 or 32 cells, will be described with reference to FIGS. 1 to 3.
FIG. 1 is a diagrammatic plan view of a memory cell array in the flash memory after a first level metal interconnection is formed. For simplification, only two first level metal interconnections 601 are shown in FIG. 1. The first level metal interconnection 601 constitutes an interconnection for backing a word line 602 in the flash memory. The word line 602 is formed of polycide. The first level metal interconnection 601 for the backing is electrically connected to the word line 602 through pillar-shaped contacts 603, which are formed at a rate of one contact per 16 or 32 cells. Reference Number 604 designates one memory cell region in the flash memory. Actually, a number of memory cell regions are formed consecutively along each word line 602, but for simplification, only one memory cell region 604 is shown in the drawing. In addition, a space for the pillar-shaped contact 603 is provided one per 16 or 32 cells.
Referring to FIG. 2, there is shown a diagrammatic sectional view taken along the line I--I longitudinally passing both the first level metal interconnection 601 and the word line 602 in FIG. 1. FIG. 3 is a diagrammatic sectional view taken along the line J--J transversely passing on the pillar-shaped contact 603 in FIG. 1. A device isolation oxide film 701 is formed on a principal surface of a semiconductor substrate 700 so as to confine a number of device formation regions (memory cell regions). This device isolation oxide film 701 is formed of a thermal oxidation film ordinarily having a thickness on the order of 400 nm.
On the principal surface of a semiconductor substrate 700 within each device formation region, a tunnel oxide film 702 is formed for example by a thermal oxidation. This tunnel oxide film 702 ordinarily has a thickness of not greater than 10 nm. A floating gate 703 is formed on the tunnel oxide film 702. For example, this floating gate 703 is formed of a polysilicon film which has a thickness on the order of 150 nm and which is lightly doped with phosphorus. Each floating gate 703 is coated with an insulating film 704, which is ordinarily formed of a triple-layer structure of oxide film/nitride film/oxide film, having a film thickness of not greater than 20 nm converted into an oxide film thickness.
The word line 602 is formed on the insulating film 704 to continuously extend over a number of floating gates 703. Therefore, the word line 602 functions as a control gate located above the floating gate 703. The word line 602 has a polycide structure formed of an underlying phosphorus-doped polysilicon layer having a thickness on the order of 150 nm and an overlying tungsten silicide layer having a thickness on the order of 150 nm. An interlayer insulator film 705 is formed to cover the whole surface including the word line 602. The first level metal interconnection 601 is formed on the interlayer insulator film 705 to extend along the corresponding word line 602, and is electrically connected to the corresponding word line 602 through a plurality of pillar-shaped contacts 603 which are provided at the rate of one contact per 16 or 32 cells and which are formed to penetrate through the interlayer insulator film 705 to reach the word line 602. Ordinarily, the first level metal interconnection 601 is formed of a triple-layer structure of TiN/Al/TiN, and the pillar-shaped contact 603 is formed of tungsten.
In the above mentioned word line structure backed with the overlying interconnection layer, however, the reading speed of the flash memory could not have been satisfactorily elevated. The reason for this is that, since the word line is electrically connected to the backing metal interconnection by only the pillar-shaped contacts which are provided at the rate of one contact per 16 or 32 cells, the resistance of the word line cannot be sufficiently lowered. In this connection, if the number of the contacts were increased in order to reduce the resistance, an extra space for providing the increased number of contacts will become necessary, resulting in an increased chip area.
In order to overcome the above mentioned problem, the co-inventors of this application proposed a new word line structure in a co-pending application entitled "NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF", filed on Sep. 2, 1999 claiming the Convention priority based on Japanese Patent Application No. 250265/1998 filed Sep. 4, 1998, assigned to the assignee of this application.
In this proposed word line structure, a groove is formed in an interlayer insulator film covering the word line (gate electrode), to longitudinally extend along the word line and to penetrate through the interlayer insulator film so as to reach the word line, and a conducting material is filled into the groove to form an upstanding-plate-shaped contact, and an overlying interconnection is formed on the upstanding-plate-shaped contact (formed of the conducting material filled in the groove), so that the word line is electrically connected to the overlying interconnection at a large contacting area by the upstanding-plate-shaped contact, thereby to reduce the resistance of the word line.
The above mentioned proposal is satisfactory to some degree from the viewpoint of reducing the resistance of the word line. In other words, it is, in some cases, necessary to further reduce the resistance of the word line, depending upon the construction and a demanded performance of the non-volatile semiconductor memory, and depending upon the shape of the contact hole and the groove and a combination of the filled metal and the interconnection metal.
The above mentioned proposal is characterized in that the groove extending in the word line direction is formed at the same time as contact holes are formed in a peripheral circuit zone of a non-volatile semiconductor memory, and the same metal is filled into the contact holes and the groove to simultaneously form pillar-shaped contacts in the peripheral circuit zone and the upstanding-plate-shaped contact in a memory zone, respectively. Thereafter, the overlying interconnection formed of a material different from that of the upstanding-plate-shaped contact is deposited on the upstanding-plate-shaped contact. Therefore, since the conducting material of the upstanding-plate-shaped contact has a resistivity larger than that of the overlying interconnection, and since a contact resistance inevitably occurs at a boundary between the overlying interconnection and the upstanding-plate-shaped contact, the resistance of the word line cannot satisfactorily be reduced.